Phase-locked loops (PLL's) may be used to generate clock signals having predetermined frequency and/or duty cycle for applications on a system-on-chip (or “SOC”). When such clocks signals are routed from the PLL output to their destinations, e.g., via clock distribution buffers, physical inter-connects, etc., there may be significant error or “skew” introduced into the duty cycle of the resulting signals. As the performance of some applications on the SOC may be sensitive to the duty cycle of the clock signals, it may be necessary to provide a duty cycle correction or adjustment circuit to correct the duty cycle of such signals prior to use in the application. Such duty cycle correction or adjustment circuits may be based on closed-loop techniques that dynamically sample and adjust the duty cycle of the clock signal.
It would be desirable to provide simple and low-power techniques for accurately adjusting periodic signals to correct for duty cycle error.